Note from the Editors
This special issue of JILP consists of a set of papers that have been carefully selected from MICRO-33 and its accompanying workshops. The papers provide an overview of quality work across diverse areas in microarchitecture and software. The selection process focused on identifying papers that represented both mature topics as well as topics of emerging importance.
In order to ensure the highest quality, each paper was reviewed by at least two experienced experts in the field. The papers were extended from the original conference and workshop versions prior to submission. Substantial improvements to address review comments were incorporated in the final manuscript. We thank both the authors and the reviewers for ensuring the technical quality and completeness of the final versions. Highlights of papers in this issue follow.
Superscalar processors dominate today’s high-performance desktop and server systems. Roth’s paper addresses inefficiencies that result because data within a superscalar processor may be unnecessarily discarded when a speculative path is mispredicted. Microprocessor memory systems are recognized as a crucial performance bottleneck. Zhang’s paper illustrates techniques that improve performance by reducing address-mapping conflicts in cache and DRAM row buffers. Improved cache writeback policies can be used to improve performance when peak memory bandwidth cannot be satisfied. Lee’s paper proposes an eager writeback scheme, that opportunistically writes dirty data back to memory when bandwidth is available. The use of centralized register files limits our ability to scale processors to exploit instruction-level parallelism. Sanchez presents work that compiles loops onto multiple register clusters to allow the construction of processors supporting additional parallelism. Microprocessor power consumption represents an increasingly important topic. Huang’s paper presents a design framework for energy management.
High-performance systems utilize software in increasingly sophisticated ways to augment capabilities provided in hardware. Multiprocessors and multithreaded machines provide an opportunity for using underutilized resources to reduce latency via data dependence speculation. Rundberg presents a compiler-based, low-overhead means of managing that speculation. History information about program execution, such as branch outcomes and common values, is finding increasing application in compilers and microarchitecture. Watterson’s paper reduces the time and space overhead for value profiling by collecting the most useful subset of data as determined by a compiler.
Chris J. Newburn and Mike Schlansker, editors